1. Field of the Invention
The present invention relates to a semiconductor device wherein a plurality of semiconductor elements are sealed with a resin.
2. Description of the Related Art
In general, one has heretofore been known as a semiconductor device, wherein a semiconductor element or chip (hereinafter called “LSI chip”) incorporating therein Large Scale Integration (hereinafter called “LSI”) in which a plurality of circuits are integrated, is sealed with a resin.
FIG. 16 is a cross-sectional view showing an internal structure of a conventional semiconductor device 1. As shown in FIG. 16, an LSI chip 3 is fixedly placed over a die 8 with an adhesive. A plurality of pad electrodes 5 placed over a main surface of the LSI chip 3 are electrically connected to their corresponding leads 9 each of which serves as a terminal for connection to the outside and is composed of a conductive material, by wires 7 used as metal thin lines or wires. The LSI chip, 3, the pad electrodes 5, the die 8, the wires 7 and parts (corresponding to portions called “inner leads”) of the leads 9, which include portions connected to the wires 7 respectively, are sealed with-an insulating resin 10. The semiconductor device 1 is electrically connected to another device by parts (corresponding to portions called “outer leads”) of the leads 9 having led out of the resin 10, e.g., with a printed wiring board interposed therebetween, whereby the transfer of signals therebetween and the like are carried out.
When the LSI chip 3 is a system LSI for implementing combined functions of a core of a central processing unit (hereinafter called “CPU”), a memory, other circuits used for peripheral functions, etc. as in the case of, for example, a microcomputer (hereinafter called “micon”) or the like, these functions are placed over the same semiconductor substrate in mixed form. Therefore, when the system LSI is equipped with a DRAM (Dynamic Random Access Memory) or a batch erasable EEPROM (Electrically Erasable Programmable Read Only Memory), a peculiar manufacturing process is required which is not included in a manufacturing process (hereinafter called “Logic process”) for implementing the CPU core and the circuits for the peripheral functions. As a result, a manufacturing process (corresponding to a process for mixing of Logic and memory) peculiar to the system LSI is applied thereto to develop products with a view toward implementing such a system LSI.
A semiconductor device in which a plurality of LSI chips are sealed with a resin to bring it to the commercial stage (i.e., a plurality of semiconductor elements are stored or held in one package), has appeared in recent years. Such a semiconductor device is referred to as “MCP (Multiple Chip Package) type”. The semiconductor device of the MCP type is applied to a memory-system LSI. The semiconductor device is applied to, for example, a case in which memories identical in type are held or accommodated in one package to implement an increase in memory capacity, or a case in which memories of types different in function from one another are held in one package to thereby implement space saving.
FIG. 17 is a cross-sectional view showing an internal structure of an MCP type semiconductor device 11. FIG. 18 is a plan view illustrating the internal structure of the MCP type semiconductor device 11. In FIGS. 17 and 18, elements of structure structurally similar to those shown in FIG. 16 are identified by the same reference numerals.
As shown in FIGS. 17 and 18, an LSI chip 3 fixedly disposed with an adhesive is placed on a die 8. A plurality of pad electrodes 5 respectively electrically connected to leads 9 by wires 7 are placed over a main surface of the LSI chip 3. Further, an LSI chip 13 is fixedly placed over the main surface of the LSI chip 3 with an insulative adhesive interposed therebetween. A plurality of pad electrodes 15 are disposed over a main surface of the LSI chip 13. These pad electrodes 15 are electrically connected to their corresponding ones of the leads 9 by wires 17. These two LSI chips 3 and 13, parts of the leads 9, which include portions where they are respectively connected to the wires 7 and 17, and the die 8 are sealed with a resin 10.
Thus, the MCP type semiconductor device 11 is configured so as to accommodate or hold a plurality of the LSI chips 3 and 13 in one package and have the leads 9 for connection to the outsides of the LSI chips 3 and 13.
As such an MCP-compatible semiconductor device 11, there is known one like BGA (Ball Grid Array), for example. This has such a structure that different types of memories such as a SRAM (Static Random Access Memory), a batch erasable EEPROM, etc. are held or stored in one package, and input/output terminals of the memories are respectively individually connected to the leads 9 to independently activate the memories respectively. Owing to such a structure, the functions corresponding to the two LSI chips can be implemented by a space for one LSI chip.
Thus, in the LSI, particularly, the system LSI built in the semiconductor device, a mixed process is applied thereto to develop products. In the memory-system LSI, the MCP type semiconductor device is applied to implement an increase in memory capacity and bring different memories into combined form, thereby developing each product.
However, the semiconductor device equipped with the system LSI has the following problems in that it is manufactured over the same semiconductor substrate according to a specific process obtained by integrating a manufacturing process peculiar to each memory into a Logic process.
A first problem is that since the number of masks increases compared with a Logic-single manufacturing process or a memory-single manufacturing process, a reduction in yield occurs. A second problem is that the specific process no allows the facilitation of an improvement in the performance of a circuit for a Logic unit and an improvement in the performance of a memory unit. A third problem is that since the manufacturing process becomes complex, TAT becomes long. A fourth problem is that since the manufacturing process is complicated and the number of masks increases, process costs are raised. A fifth problem is that the development itself of a process used for LSI obtained by mixing an LSI comprising an SOI (Silicon On Insulator) process which purses a low voltage/low current operation and an LSI comprising a special process for fabricating high-withstand elementary devices (high-withstand MOS transistors, etc.) together is so difficult from a technical viewpoint.
In an LSI to which a finer deep sub-micron manufacturing process is applied, a reduction in voltage (about 0.8V to 1.5V) is accelerated even in a Logic process from now on in particular. Thus, a plurality of voltages including a high voltage (e.g., 8V to 12V) higher than a source voltage (e.g., 3.3V or 5V) are required upon rewriting and reading of data as in the case of the batch erasable EEPROM. It is therefore difficult to implement a system LSI (such as a batch erasable memory-equipped micon or the like) configured by integrating a high-withstand process for building high-withstand elementary devices therein and the Logic process therein.
Since the MCP type semiconductor device aims. to increase the capacity of each memory and provide space saving as described above, limitations are imposed on the provision of leads for each individual LSIs to accommodate or hold the same types of memory system LSIs in one package or hold different types of memory system LSIs in one package and independently operate the different types of memory system LSIs respectively. Therefore, nothing was found to implement the system LSI for the MCP type semiconductor device.
The present invention aims to solve the above problems and make it possible to easily implement a system LSI by a semiconductor device wherein a plurality of LSI chips are sealed with a resin.
Further, the present invention aims to solve problems developed upon implementation of a system LSI by a semiconductor device wherein a plurality of LSI chips are sealed with a resin, and implement the system LSI without impairing a function defined as for the system LSI as compared with the prior art.